Regviz

Espressif Systems /ESP32-C6 /EXTMEM /L1_ICACHE3_PRELOCK_CONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as L1_ICACHE3_PRELOCK_CONF

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-C6/EXTMEM/L1_ICACHE3_PRELOCK_CONF#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE3_PRELOCK_SCT0_EN)L1_ICACHE3_PRELOCK_SCT0_EN 0 (L1_ICACHE3_PRELOCK_SCT1_EN)L1_ICACHE3_PRELOCK_SCT1_EN 0L1_ICACHE3_PRELOCK_RGID

Description

L1 instruction Cache 3 prelock configure register

Fields

L1_ICACHE3_PRELOCK_SCT0_EN

The bit is used to enable the first section of prelock function on L1-ICache3.
L1_ICACHE3_PRELOCK_SCT1_EN

The bit is used to enable the second section of prelock function on L1-ICache3.
L1_ICACHE3_PRELOCK_RGID

The bit is used to set the gid of l1 icache3 prelock.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data